Conventionally, a semiconductor memory device such as a DRAM has been widely used as a main memory for a personal computer or a mini-computer. The DRAM is generally controlled on the basis of various control signals such as CAS (column address select) signal obtained by processing a clock supplied to operate a CPU. In other words, the clock signal used for the CPU cannot be used as it is; that is, the clock for operating the CPU has been so far processed for controlling the memory device.
With the advance of the semiconductor technology, however, the operating frequency of the CPU has recently become higher than that of the DRAM. Therefore, in order to prevent the operating speed of the CPU from being affected by the operating speed of the DRAM, there has been required such complex memory control as using a plurality of assembled DRAMs interleaved therebetween.
In the case of a relatively small-scale system such as a mini-computer, work station, etc., however, when a number of memory devices are used under interleaved condition, there exists such a disadvantage that the control system of the memory device becomes complicated and therefore the system cost increases. In addition, since the operating frequency of the CPU has been increased up to 50 MHz and further to 100 MHz, it is necessary to construct the memory device hierarchically, thus raising a problem in that the control of the memory system becomes increasingly complicated, thereby increasing the system load.